Memory systems are known in the art and used in nearly all micro-processor and digital equipment applications. Memory systems generally utilize different types of memory for different applications. Once such type of memory is Static Random Access Memory ("SRAM"). SRAM systems have the advantage of high speed and ease of use as compared to some other types of memory systems. In addition, SRAM systems using MOS technology exhibit extremely low standby power and do not require a refresh cycle to maintain the information stored in the SRAM system. These attributes make SRAM systems particularly desirable for portable equipment, such as laptop computers.
In an integrated circuit, SRAM systems are often organized into an array of memory cells, arranged in rows and columns. Generally, memory cells are set to one of two data states when storing a bit of information. Each memory cell may be referenced by a unique memory address, which includes a row address and a column address. The term "wordline" generally refers to one or more conductors that correspond to a row of memory cells, whereas the term "bitlines" generally refers to a set of conductors that correspond to a column of memory cells. A memory cell typically includes of pair of complementary ports, with each port connected to one of the two bitlines dedicated to that column. Memory devices commonly operate in a read mode and a write mode. When writing to a memory cell, the wordline is activated, thereby activating the entire row in the array of memory cells. A differential current is applied to the bitlines between the two complementary input/output ports of the memory cell. The memory cell is latched to a specific logic state with a logic high indicated on one port and a logic low indicated on the other port. When reading from a memory cell, the wordline is activated and the logic states on the bitlines associated with the memory cell is differentially sensed using a sense amplifier. The sense amplifier outputs an amplify signal corresponding to the logic state written to the memory cell.
A typical six transistor SRAM memory cell consists of two p-ch pull-up transistors, two n-ch pull-down transistors and two access transistors which are typically n-ch.
High read current, write trip voltage and static noise margin, and low standby current are desired cell characteristics of a SRAM cell. High read current and write trip voltages are needed to improve the speed at which the data can be accessed and written, respectively. High static noise margin is needed for the circuit stability. Low standby current is needed to lower the power consumption when the cell is in the standby mode. Low standby current is achieved by keeping the threshold voltages of the various transistors high so that the subthreshold leakage current can be minimized. Increasing the n-channel threshold voltages, however, reduces the drive current and, hence, the read current during a read operation. It also reduces the write voltage, which results in slower write operations. Also, increasing the p-channel threshold voltage reduces the static noise margin, which hampers cell stability. Thus, a tradeoff exists between the low standby current and the speed and stability of the cell. The problem becomes more severe for lower supply voltages when the threshold voltage is a large fraction of the supply voltage, e.g., the case when the supply voltage is approximately one volt.
A conventional solution to this problem has been to increase the internal supply voltage for the SRAM array to a maximum limit determined by gate oxide thickness and the device reliability. The problem with this type of biasing scheme is that the high voltage level can be very inefficient from the power consumption point of view. Also, because this boosted voltage would be applied to the bitlines, a large amount of supply current is needed to operate the SRAM array and poses difficulties in generating the boosted power.
Another conventional solution to speed up the read and write operation has been to boost the wordline voltage over the bitline and array supply. However, this approach has the disadvantage of lowering the static noise margin and hence the stability of the cell.
Another conventional solution has been to step down the bitline voltage to be lower than the supply voltage. Again, this method may or may not save power depending upon the bitline voltage level and how it is step down.